Existing standard cell library constructs provide competitive cell area and density. Among those cell library constructs is a pass-through contact used in more advanced technology nodes. As technology continues to produce smaller semiconductor devices, the spacing between middle-of-line (MOL) layers decreases. This leads to congestion of MOL and back-end-of-the-line (BEOL) layers, such as metal 1 (M1) to gate contact (CB) spacing in fully depleted silicon-on-insulator (FD-SOI) technology, source/drain contact (CA) to CB spacing for 20 low power mobile (LPM) computing applications, or trench silicide (TS) to CB spacing in 20 LPM computing applications. Also, in order to meet spacing requirements for manufacturability and reliability, other design rules such as CB to gate (PC) contact are compromised.
M1 to CB spacing in a current FD-SOI is 40 nm (minimum rule). This limits laterally flipping the cells for the library design which leads to M1 congestion. M1 jogs are also required, and this introduces corner rounding and leads to M1 congestion as well. Further, with 20 LPM computing applications a CB offset is used which reduces CB-PC contact area, and there is a risk of an open CB-PC, which leads to a high risk construct. With 20 LPM computing applications a CA was used instead of M1, and the CA needs to be narrow to enable this library construct for production level.
A need therefore exists for methodology enabling the formation of a pass-through contact that helps reduce MOL congestion without compromising design rules, and the resulting device.